1. Field of the Invention
The present invention relates to a phase change type nonvolatile memory (hereinbelow referred to as a PRAM: phase change random access memory) and a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-193560, filed Jul. 25, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
There is a variety of memory devices which are constituted hierarchically, used in a personal computer, a server and the like. The memory device which is assigned to a lower hierarchy is required to be cheap and have mass storage capacity, while the memory device which is assigned to a higher hierarchy is required to have high access speed. Magnetic storages such as a hard disk drive and a magnetic tape are generally used in the memory devices which are assigned to the lowest hierarchy. The magnetic storage is nonvolatile and able to have a much larger data capacity than a semiconductor memory, with a low cost. However, the access speed of the magnetic storage is slow and the magnetic storage does not possess random accessness in many cases. For this reason, a program, data which is stored for a long term, and the like are stored in the magnetic storage so as they are transferred to the memory device, to order, which is assigned to the higher hierarchy.
A main memory is the memory device which is assigned to the higher hierarchy than the magnetic storage. In general, a dynamic random access memory (DRAM) is used as the main memory. The DRAM enables to high speed access when compared with the magnetic storage, and has random accessness. Furthermore, the DRAM has a character that has a lower cost per bit than that of high speed semiconductor memories such as a static random access memory (SRAM) and the like.
An integrated cache memory which is integrated in a micro processing unit (MPU) is assigned to the highest hierarchy. Since the integrated cache memory is connected with a core of the MPU via an inner bus, the integrated cache memory provides significantly higher access speed. However, the capacity of the integrated cache memory is quite small. A second cache, a third cache and the like might be used as the memory device that constitutes the hierarchy between the integrated cache memory and the main memory.
The reason that the DRAM is selected as the main memory is a significant good balance of the access speed and the cost per bit. Moreover, the DRAM provides the mass storage capacity among the semiconductor memories. Recently a DRAM chip having a capacity over 1 Gbit has been developed. However, since the DRAM is volatile, the stored data is deleted when a power supply unit turns off. For this reason, the DRAM is inadequate to store the program and the data which is stored for the long term. When the power supply is turned on, a refresh operation is regularly required to maintain the data. Therefore, a reduction in the power consumption is limited, and there is a necessity of complex control by a controller.
A flash memory is known as the volatile semiconductor memory having mass storage capacity. However, the flash memory needs to load a high current for writing and deleting the data. Moreover, the flash memory has a demerit for which writing time and deleting time are quite long. Therefore, it is inadequate to substitute the flash memory for the DRAM as the main memory. Although, in regard to the nonvolatile memories, a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM) and the like are proposed, it is difficult to obtain a comparable storage capacity to the DRAM.
On the other hand, the PRAM that records in phase change materials is proposed as the semiconductor memory instead of the DRAM (for example, refer to Japanese Unexamined Patent Applications No. 2006-165560, No. 2007-73779, and No. 2003-163280). The PRAM stores the data by using a phase state of the phase change materials which are included in a recording layer. That is, since an electrical resistance of the phase change materials is significantly different according as the phase change materials assume a crystalline phase or an amorphous phase, the PRAM enables recording of the data by using this electrical resistance difference.
The phase state change is induced by heating the phase change materials through a writing current application. The data reading in which the value of the reading current, or measuring current, is set to be enough lower than the writing current to be able to protect the phase state change, is performed by measuring the electrical resistance of the phase change materials. Therefore, the phase state of the phase change materials is unchanged unless a high temperature is applied so the data is maintained even if the power supply is turned off.
In order to heat the phase change materials effectively through the writing current, it is useful to narrow a current pass as small as possible by focusing a heat region (heat spot) on the recording layer.
As set forth, in the PRAM, the phase change materials change the phase state from the crystalline phase to the amorphous phase, and vice verse, by use of the heat that is generated at a contact interface between a heat plug and the recording layer when the current is applied to the heat plug. The current which is necessary for the phase change process from the crystalline phase to the amorphous phase is called “Ireset”.
In the conventional PRAM, as shown in FIG. 33, a heat plug 201 is embedded into a pore 203 passing through an interlayer insulating layer 202. A recording layer 204 which is formed on the interlayer insulating layer 202 is heated by the heat plug 201 with a diameter of the pore 203. In this case, a contact diameter φ′ between the heat plug 201 and the recording layer 204 is limited to around 100 to 160 nm, due to a process limit of the pore 203 by using a lithographical technology. Since the lower limit of Ireset depends on a contact area π×(φ′/2)2 between the heat plug 201 and the recording layer 204, the Ireset is inapplicable smaller than that at the process limit of the pore 203.
For this reason, it is proposed for the PRAM, as shown in FIG. 34, that a sidewall 205 is provided on an inner wall of the pore 203 so as the contact diameter φ′ between the heat plug 201 and the recording layer 204 further decreases. In this case, however, there is a limit of decreasing the contact diameter φ′ between the heat plug 201 and the recording layer 204. In the case of the sidewall 205 being thicker, since a micro-loading effect becomes predominant, an etch-back becomes difficult when the sidewall 205 is formed. In this case, due to productive failures such as an incomplete etching and the like, the process limit of φ′ has been considered around 30 nm so far.
In order to further increase the capacity of the PRAM, the Ireset should be decreased by decreasing the contact diameter φ′ between the heat plug 201 and the recording layer 204. However, in the conventional PRAM, since decreasing the contact diameter φ′ between the heat plug 201 and the recording layer 204 is restricted by the process limit of the pore 203 and the sidewall 205, the Ireset is inapplicable smaller than that at the process limit. The heat plug 201 is generally composed of metals having a high thermal conductivity. If a heat-sink effect of the heat plug 201 becomes predominant, the Ireset should be further larger. Therefore, in order to heat the phase change materials (change the phase state) by the much smaller Ireset, it is necessary to narrow a current pass as small as possible by focusing the heat region (heat spot) on the recording layer.